Bonded wires and solder bumps are common microstructures formed on micro devices, which are usually fabricated on silicon wafers. Wire bonding is the earliest technique for interconnecting electronic devices. However, many potential issues exist in the bonded wires, for example, weak bond and heel crack.
PoP technology is an important development for the microelectronic industry. PoP packaging using the solder bump with a large size has excellent yield. As the pitch of solder bumps in PoP packaging decreases, it may result in high bridge risk. In addition, the solder bump may be collapse during reflow soldering. Accordingly, there is a need to provide an alternative interconnect structure to address the problems mentioned above.